TELEMAC: An efficient hydrodynamics suite for massively parallel architectures

The Challenges of Efficient Code-Generation for Massively Parallel Architectures

Overcoming the memory wall [15] may be achieved by increasing the bandwidth and reducing the latency of the processor to memory connection, for example by implementing Cellular architectures, such as the IBM Cyclops. Such massively parallel architectures have sophisticated memory models. In this paper we used DIMES (the Delaware Iterative Multiprocessor Emulation System), developed by CAPSL at ...

An Architecture Description Language for Massively Parallel Processor Architectures

In this paper, we introduce an architecture description language for modeling, simulation, and evaluation of massively parallel processor architectures that are designed for special purpose applications from the domain of embedded systems. The architectural description of the processor system is supposed to be done according to two abstraction levels. Architectural parameters of processor eleme...

High Performance Networks for Massively Parallel Architectures

The past few years have seen a rise in popularity of massively parallel architectures that use fat-trees as their interconnection networks. In this paper we study the communication performance of a parametric family of fat-trees, the k-ary n-trees, built with constant arity switches interconnected in a regular topology. Through simulation on a 4-ary 4-tree with 256 nodes, we analyze some varian...

Compiling FORTRAN for Massively Parallel Architectures

Compiling for massively parallel architectures: a perspective

The problem of automatically generating programs for massively parallel computers is a very complicated one, mainly because there are many architectures, each of them seeming to pose its own particular compilation problem. The purpose of this paper is to propose a framework in which to discuss the compilation process, and to show that the features which aaect it are few and generate a small num...